A suite of software verification tools is frequently used as part of a test environment during the development of application specific integrated circuits (ASICs). Prior to committing an ASIC design to silicon, it is common to run a suite of simulations of the ASIC device to verify that the design will function as intended. Often, developers convert portions of this suite of simulation tools from other projects in order to shorten development time.
A problem that sometimes arises in the testing of ASICs designed to generate signals in the Sony/Philips Digital Interconnect Format (SPDIF) involves access to a clock for the data contained within the SPDIF signal. The SPDIF signal is composed of clock and data encoded as a single signal. An engineer involved in the testing of an ASIC generating an SPDIF compliant signal may have software used in testing another SPDIF-related ASIC design. That software may be capable of checking the SPDIF signal generated by the ASIC being simulated. However, due to the fact that the SPDIF signal contains its own clock signal, the software used for testing the simulated SPDIF signal typically requires a clocking signal from within the code simulating the new ASIC device design. The designer may therefore be forced to locate, or in a worst case scenario, synthesize a suitable clocking signal from signals within the ASIC design simulation software for each ASIC design, for use by the simulation software used to verify the SPDIF signal.
A second problem frequently appears once the data carried by the SPDIF signal is recovered. A SPDIF subframe contains a number of types of data, some having no defined timing relationship to others. This complicates testing, in that changes in the ASIC design that result in the generation of a valid SPDIF signal may be misinterpreted by existing design verification tools as representing an error. Currently available verification tools collect the sequence of output transitions and compare them to a “golden” reference file. Each line of output of a present day SPDIF verification tool may contain the following data elements from an SPDIF subframe:                1. subframe preamble        2. audio sample payload        3. channel status bit (C)        4. validity bit (V)        5. user data bit (U)        6. parity bit (P)        
Often, in the process of porting a test to a new design, element [2] may be shifted in time relative to elements [1], [3], [4], and [5]. This may cause element [6] to mismatch and made it impossible to find matching lines between the new design output and the “golden” or reference file. This may happen even in cases where each of the individual elements match the reference file contents and the overall design is functioning properly.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.